The present invention relates to a stacked semiconductor package and a method for manufacturing the same.
In the semiconductor industry, packaging technologies for semiconductor integrated circuits have continuously are being developed to meet the demands toward miniaturization and mounting efficiency. For example, the demand for miniaturization is accelerating the development of technologies for a package having a size approaching to that of a chip, and the demand for mounting reliability is highlighting the importance of packaging technologies for improving the efficiency of mounting work and mechanical and electrical reliability after mounting. Also, as miniaturization and high performance are demanded in electric and electronic products, stacking technologies have been suggested in the art and are currently being developed into various styles.
The term “stack” referred to in the semiconductor industry means a technology of vertically piling at least two semiconductor chips or semiconductor packages. By using the stack technology, for example, a 512M DRAM may be configured by stacking two 256M DRAMs. Further, since a stacked semiconductor package provides advantages in terms of memory capacity, mounting density and mounting area utilization efficiency, search and development of stacked semiconductor packages are being accelerated.
FIG. 1 is a cross-sectional view illustrating a known POP (Package On Package) type stacked semiconductor package. A lower package 20 and an upper package 30 are stacked on a main substrate 10 while electrically connected by solder balls 41 and 42.
In detail, the main substrate 10 and the lower package 20 are electrically connected with each other by the solder balls 41 which are formed between ball land patterns 11 formed on the upper surface of the main substrate 10 and ball land patterns 23A formed on the lower surface of a substrate 21 of the lower package 20, and the lower package 20 and the upper package 30 are electrically connected with each other by the solder balls 42 which are formed between ball land patterns 23B formed on the upper surface of the substrate 21 of the lower package 20 and ball land patterns 33 formed on the lower surface of a substrate 31 of the upper package 30.
The unexplained reference numerals 22, 24, 25 and 26 respectively designate a first semiconductor chip, a first adhesive member, first bonding wires and a lower mold part which constitute the lower package 20, and the unexplained reference numerals 32, 34, 35 and 36 respectively designate a second semiconductor chip, a second adhesive member, second bonding wires and an upper mold part which constitute the upper package 30.
However, in the known stacked semiconductor package, warpage may occur in the main substrate 10, the lower package 20 and the upper package 30 when performing a reflow process for the solder balls 41 and 42, and due to the occurrence of warpage, cracks may occur in the solder balls 41 and 42. The occurrence of cracks may lead to the occurrence of fails, whereby the manufacturing yield and the productivity may deteriorate.